Modern types of writable RAM generally store data in either the state of a flip flop, as in static RAM (“SRAM”), or as a charge in a capacitor (or transistor gate), as in dynamic RAM (“DRAM”). DRAM stores each bit of data in a separate capacitor within an integrated circuit. A basic DRAM cell is shown in FIG. 1; it comprises of one transistor and one capacitor.
DRAM was invented in 1966 by Dr. Robert Dennard and he was awarded US Patent in 1968 (U.S. Pat. No. 3,387,286). Since this time, the basic DRAM device has consisted of a single transistor and increasingly complex capacitors.
There are several problems associated with the capacitor design. First, because capacitors leak, the data stored in a capacitor will be lost unless the capacitor is refreshed periodically. Second, scaling a capacitor creates larger current leakage. The limiting factor in the basic capacitor/transistor building block is the capacitor.
Cell capacitance is the key parameter used to determine sensing signal margin, sensing speed, data retention time and endurance against soft error. It is generally accepted that the minimum cell capacitance should be 25 fF/cell regardless of minimum feature size, density, and chip size. The requirement of memory cell capacitance over 25 fF/cell is a practical design guideline rather than a theoretical limit. This requirement imposes a great challenge on giga-bit scaled DRAMs because capacitor area is scaled down with the square of the minimum feature size. Capacitors can be fabricated as high stacks or deep trenches. However, if the overall memory size shrinks because of increased density or a smaller process node, then the capacitor will have to be made higher or deeper in order to maintain the minimum charge required for reliable operation. We are fast approaching scaling limits for the capacitor.